FPGA consultant ID:405

 Requirements:

·                 4+ years of experience in HDL design in a multi-clock environment for FPGA implementation

·                 Linux experience

·                 System Verilog as main HDL 

·                 Worked with medium to large designs 

·                 Experience of designing and working with fully custom, in-house built System Verilog modules 

·                 Experience of working with integration and configuration of FPGA Vendor IPs

·                 Optimization of calculation heavy algorithms on RTL level

·                 STA analysis and requirements 

o              Experienced in timing-critical FPGA design and timing closure

o              Experience in writing timing constraints for multi-clock domain designs

·                 Verification using System Verilog and Python

·                 Worked with SOC FPGAs, i.e. with hardened CPU

·                 High speed IO, DDR , PCIe and MIPI

·                 AMD Xilinx tool chain

·                 Board bring-up & debugging 

o              Use of Vivado ILA  

·                 Scripting, mainly in Python 

·                 Electronics and Electronic lab tools fundamentals (Multimeter, Osciloscope) 

·                 Digital Signal Processing fundamentals 

·                 Comfortable with simulation tools and writing testbenches

·                 Good at documenting full designs

Good to have:

·                 Altera tool chain

·                 Experience of High Level Synthesis 

·                 Experience of MATLAB and Simulink

·                 AMD Xilinx Vitis model composer

·                 VCS 

·                 Fixed Point design skills 

·                 AMD Zynq UltraScale+ 

·                 AMD VITIS Model Composer 

·                 Radio Algorithm Implementation 

·                 Wireless Communications

·                 git

Personality:

·                 Open and solution oriented

·                 Easy to work with

 100% onsite